Korean Patent Application publication KR 10-2009-0029582 teaches a method for forming open trenches to a solder mask layer on a surface of a printed circuit board.
U.S. Patent Application publication US 2010/0084748 teaches methods for minimizing warpage of a welded foil carrier structure used in the packaging of integrated circuits. The methods concentrate to solve warpage by affecting to the features of a metallic foil or manufacturing related them.
The main problem in the prior art is that warpage is still a major problem during the manufacturing process of the electronic circuit boards and especially, when manufacturing non-symmetrical circuit board structures with heat and pressure treatment.